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   COLLOQUIUM OF THE LABORATORY FOR COMPUTER DESIGN OF MATERIALS
                   School of Computational Sciences
                           (CSI 898-Sec 001)
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	Silicon on Insulator (SOI): Technology and Nanodevices

                            Dimitrios E. Ioannou
                 ECE Department, George Mason University

The most common Silicon on Insulator (SOI) wafer fabrication technologies will
be described, along with the properties and quality of the corresponding SOI
wafers. Then the basic device physics of the SOI MOSFET will be covered, both
for partially-depleted (PD) and fully-depleted (FD) operation. Unique features
of these structures such as channel coupling and floating body effects will be
explained, and this will be followed by a discussion of how these features
impact performance reliability. Finally some of the latest applications of SOI
technology in the fabrication of nanostructures will be presented and an
attempt will be made to highlight potential research opportunities in the area
of new SOI semiconductor nanodevices.
                         
                        Monday , October 25, 2004
                                  4:30 pm
               Room 206, Science & Tech. I, Fairfax Campus
                                
Refreshments will be served at 4:15 PM.
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Find the schedule at http://www.scs.gmu.edu/lcdm/seminar/schedule.html
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